With the advent of the BiMOS/BiCMOS technologies and much demand for analog signal processing functions in the MHz ranges, the analog designers are challenged to design circuits that outperform the very few available bipolar, only high frequency, circuit building blocks. The widely acceptable bipolar frequency multiplier is the Gilbert frequency multiplier which relies on current switching. The frequency multiplication of the Gilbert circuit is essentially based on the conversion of the carrier frequency to switching currents and execratively multiplying it to the multiplicand signal. The output of this circuit, at best, includes all of the odd harmonic carrier components, hence requiring a filtering function to select the desired output. The presented circuit of this disclosure tries to minimize the harmonic contents of the output and therefore tends to eliminate the usually required filtering functions while maintaining the high speed operation.
The recently developed v-i converter/frequency multipliers in MOS technologies have very limited frequency range of operation. Almost all of these circuits imitate the Gilbert multiplier circuit.
Some efforts in realizing BiCMOS circuits for analog-to-digital converters have been started. In this report, we attempt to disclose a BiCMOS v-i/frequency multiplier cell that incorporates bipolar and MOS devices for maximum performance and frequency of operation. This cell can be utilized as a building block in the realization of many analog functions such as phase/vector-lock-loops, modulators/demodulators, variety of analog signal processors for radio/TV applications and etc.
We first attempt to explain the design of the cell followed by the derivation of expressions describing the functions of the proposed cell. We then provide some computer simulation results representing the functional behavior of this cell. Finally, some experimental results of a simplified breadboarded version of this cell will be provided.